1. Field of the Invention
The present invention relates to a surge absorption circuit with an improved high-frequency characteristic.
2. Related Background of the Invention
Since semiconductor devices such as IC and LSI are destroyed or caused to deteriorate their properties by high-voltage static electricity, surge absorbing devices such as varistors have been in use as measures against static electricity. The surge absorbing devices such as varistors have a stray capacitance component and an equivalent series inductance component, and thus deteriorate signals when employed in circuits dealing with high-speed signals.
FIG. 1 is a diagram showing an example in which a varistor is employed in a surge absorption circuit. A surge absorption circuit 100 shown in FIG. 1 comprises an I/O terminal 101, a common terminal 102, and a varistor 103. When an input signal having a small amplitude is fed to the I/O terminal 101, the varistor 103 keeps its high resistance and does not affect the input signal. On the other hand, a high-voltage surge fed to the I/O terminal 101 is let out to the common terminal 102 by the varistor 103. As a result, connecting the surge absorption circuit shown in FIG. 1 to an I/O terminal of a semiconductor device protects the semiconductor device against high-voltage surges.
FIG. 2 is a diagram showing an equivalent circuit of a varistor. As shown in FIG. 2, the varistor can be expressed equivalently by a variable resistor 104 and a stray capacitance 105, provided in parallel between one terminal and the other terminal. The variable resistor 104, which usually has a large resistance value, reduces the resistance value when a high-voltage surge is applied thereto, thereby protecting the semiconductor device against the high-voltage surge. Since the stray capacitance 105 exists, however, high-speed signals deteriorate when the varistor is added to the I/O side of a semiconductor device dealing with the high-speed signals.
FIG. 3 is a diagram showing the calculation result of S parameters S11 and S21 of the surge absorption circuit expressed by the equivalent circuit shown in FIG. 2. FIG. 3 shows the S parameters S11 and S21 when the capacitance Cz of the stray capacitance is 1 pF, 3 pF, and 5 pF, respectively. In the case where the stray capacitance 105 is 5 pF, S21 begins to deteriorate when the frequency exceeds several hundred MHz, whereby signals cannot be transmitted anymore. S11 also increases, thereby deteriorating the reflection characteristic. The same holds when the frequency exceeds 1 GHz at the stray capacitance 105 of 1 pF. The stray capacitance has a tradeoff relationship to a clamping voltage and a surge durability, which is problematic in that surge absorbing devices having a favorable characteristic for high-speed signals cannot be employed.
FIG. 4 is a diagram showing the TDR (Time Domain Reflectmetry) test result of a conventional surge absorption circuit. FIG. 4 shows TDR when the capacitance Cz of the stray capacitance is 1 pF, 3 pF, and 5 pF, respectively. When the stray capacitance is 5 pF, the input impedance with respect to a pulse signal having a rise/fall time of 200 ps and a signal amplitude of 1 V0-p decreases to about 40 Ω with respect to a steady state of 100 Ω. It decreases to about 80 Ω even when the stray capacitance is 1 pF.
Thus, for employing a surge absorption circuit in a circuit dealing with a high-speed signal, the rising characteristic and delay characteristic of the high-speed signal must deteriorate unless the stray capacitance component is made smaller. On the other hand, reducing the stray capacitance component of the surge absorbing device raises the clamping voltage of the surge absorbing device and decreases its surge durability.
Surge absorption circuits which alleviate influences of the stray capacitance component have already been proposed. For example, combining an inductor device with a surge absorbing device can achieve impedance matching in the surge absorption circuit. FIG. 5 is a diagram showing an example of a conventional surge absorption circuit in which two inductor devices are combined with a varistor. In a surge absorption circuit 110 shown in FIG. 5, two inductor devices 114 and 115 are connected in series between an input terminal 111 and an output terminal 112, whereas a varistor 116 is connected between a midpoint of the series circuit and a common terminal 113.
FIG. 6 is a diagram showing another example of a conventional surge absorption circuit in which an inductor device is combined with two varistors. In a surge absorption circuit 120 shown in FIG. 6, a varistor 123 is connected in series to a parallel circuit of a varistor 124 and an inductor device 125 between an I/O terminal 121 and a common terminal 122. Such a surge absorption circuit is disclosed in, for example, Japanese Patent Application Laid-open No. 2001-60838.